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RT8869A 1 ds8869a-00 may 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. advanced 2/1-phase pwm controller for cpu core power applications z desktop cpu core power z middle/high end graphic cards z low voltage, high current dc/ dc converters pin configurations wqfn-40l 5x5 (top view) features z z z z z 12v power supply voltage z z z z z 2/1-phase power conversion z z z z z integrated 2 mosfet drivers with internal bootstrap diode z z z z z dynamic phase control capability z z z z z 8-bit dac supports intel vr11.x cpus z z z z z lossless r ds(on) current sensing for current balance z z z z z adjustable frequency : 50khz to 1mhz z z z z z adjustable over current protection z z z z z adjustable soft-start z z z z z vr_rdy, vr_hot and vr_shdn indications z z z z z small 40-lead wqfn package z z z z z rohs compliant and halogen free marking information RT8869Azqw : product number ymdnn : date code general description the RT8869A is an advanced 2/1-phase synchronous buck controller with 2 integrated mosfet drivers. it integrates an 8-bit dac that supports intel vr11.x cpus power application. the ic adopts state-of-the-art dynamic phase control capability by ps1 pin and achieves high efficiency over a wide load range. it uses lossless r ds(on) current sensing to achieve phase current balance. other features include adjustable operating frequency, adjustable soft-start, short circuit protection, adjustable over current protection, over voltage protection, under voltage protection, power good indication, vr_hot indication and vr_shdn indication. the RT8869A is available in a small footprint with wqfn- 40l 5x5 package. vrsel en ss csn csp comp fb dac eap vr_rdy ugate1 vcc12a lgate1 vr_hot boot2 ugate2 phase2 vcc12b lgate2 phase1 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 imax ps1 isen2 isen1 rt vcc5 tb vout tm fbrtn vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 boot1 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 41 gnd vr_shdn package type qw : wqfn-40l 5x5 (w-type) RT8869A lead plating system z : eco (ecological element with halogen free and pb free)) RT8869A zqw ymdnn
RT8869A 2 ds8869a-00 may 2011 www.richtek.com typical application circuit u g a t e 1 u g a t e 2 e a p r t 8 8 6 9 a b o o t 2 l g a t e 1 s s p h a s e 2 v o u t c o m p f b r t n b o o t 1 p h a s e 1 l g a t e 2 d a c load f b v i d [ 7 : 0 ] v r s e l v r _ r d y p s 1 c s n n t c 2 t m i m a x 2 31 30 29 28 25 24 23 22 1 10 40 3 8 7 13 20 11 5 6 19 12 32 to 39 v r _ h o t 21 c 2 9 l 1 v i n r 3 c 2 r 4 r 5 q 1 q 2 i s e n 1 15 r 3 8 c 7 c 3 l 2 r 7 c 5 r 8 r 9 q 3 q 4 i s e n 2 14 r 3 7 c 8 c 6 c 3 0 c 9 r 1 0 c 1 0 r 1 1 c 1 1 r 1 2 c 3 3 c 1 2 c 1 3 c 1 4 r 2 c 1 r 1 c 2 6 r 2 9 t b 18 r 1 8 v s h d n v c c 5 r 1 9 q 9 r 2 0 r 2 1 v v r _ s h d n n t c 1 r 2 3 c 5 r 2 4 r 3 0 p h 1 r 3 1 p h 2 c s n + c s p 9 v c c 5 17 c 2 3 r 1 7 v t t v v r _ h o t r p s 1 c 1 7 e n 4 chip enable v v r _ r d y r 6 c 4 4 . 5 v t o 1 3 . 2 v r 4 0 c s n + c 3 4 r 1 3 r 1 4 v c o r e v i n 4 . 5 v t o 1 3 . 2 v r 4 1 c s n + r 3 5 v t t v c c _ s n s v s s _ s n s v c c _ s n s r t 16 r r t v c c 1 2 a g n d 1 2 v 4 1 ( e x p o s e d p a d ) 27 26 r 1 5 c 1 5 v c c 1 2 b r 1 6 c 1 6 v r _ s h d n
RT8869A 3 ds8869a-00 may 2011 www.richtek.com table 1. vr11.1 vid code table vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 0 0 0 0 0 0 0 0 off 0 0 0 0 0 0 0 1 off 0 0 0 0 0 0 1 0 1.60000 0 0 0 0 0 0 1 1 1.59375 0 0 0 0 0 1 0 0 1.58750 0 0 0 0 0 1 0 1 1.58125 0 0 0 0 0 1 1 0 1.57500 0 0 0 0 0 1 1 1 1.56875 0 0 0 0 1 0 0 0 1.56250 0 0 0 0 1 0 0 1 1.55625 0 0 0 0 1 0 1 0 1.55000 0 0 0 0 1 0 1 1 1.54375 0 0 0 0 1 1 0 0 1.53750 0 0 0 0 1 1 0 1 1.53125 0 0 0 0 1 1 1 0 1.52500 0 0 0 0 1 1 1 1 1.51875 0 0 0 1 0 0 0 0 1.51250 0 0 0 1 0 0 0 1 1.50625 0 0 0 1 0 0 1 0 1.50000 0 0 0 1 0 0 1 1 1.49375 0 0 0 1 0 1 0 0 1.48750 0 0 0 1 0 1 0 1 1.48125 0 0 0 1 0 1 1 0 1.47500 0 0 0 1 0 1 1 1 1.46875 0 0 0 1 1 0 0 0 1.46250 0 0 0 1 1 0 0 1 1.45625 0 0 0 1 1 0 1 0 1.45000 0 0 0 1 1 0 1 1 1.44375 0 0 0 1 1 1 0 0 1.43750 0 0 0 1 1 1 0 1 1.43125 0 0 0 1 1 1 1 0 1.42500 0 0 0 1 1 1 1 1 1.41875 0 0 1 0 0 0 0 0 1.41250 0 0 1 0 0 0 0 1 1.40625 0 0 1 0 0 0 1 0 1.40000 vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 0 0 1 0 0 0 1 1 1.39375 0 0 1 0 0 1 0 0 1.38750 0 0 1 0 0 1 0 1 1.38125 0 0 1 0 0 1 1 0 1.37500 0 0 1 0 0 1 1 1 1.36875 0 0 1 0 1 0 0 0 1.36250 0 0 1 0 1 0 0 1 1.35625 0 0 1 0 1 0 1 0 1.35000 0 0 1 0 1 0 1 1 1.34375 0 0 1 0 1 1 0 0 1.33750 0 0 1 0 1 1 0 1 1.33125 0 0 1 0 1 1 1 0 1.32500 0 0 1 0 1 1 1 1 1.31875 0 0 1 1 0 0 0 0 1.31250 0 0 1 1 0 0 0 1 1.30625 0 0 1 1 0 0 1 0 1.30000 0 0 1 1 0 0 1 1 1.29375 0 0 1 1 0 1 0 0 1.28750 0 0 1 1 0 1 0 1 1.28125 0 0 1 1 0 1 1 0 1.27500 0 0 1 1 0 1 1 1 1.26875 0 0 1 1 1 0 0 0 1.26250 0 0 1 1 1 0 0 1 1.25625 0 0 1 1 1 0 1 0 1.25000 0 0 1 1 1 0 1 1 1.24375 0 0 1 1 1 1 0 0 1.23750 0 0 1 1 1 1 0 1 1.23125 0 0 1 1 1 1 1 0 1.22500 0 0 1 1 1 1 1 1 1.21875 0 1 0 0 0 0 0 0 1.21250 0 1 0 0 0 0 0 1 1.20625 0 1 0 0 0 0 1 0 1.20000 0 1 0 0 0 0 1 1 1.19375 0 1 0 0 0 1 0 0 1.18750 0 1 0 0 0 1 0 1 1.18125 to be continued
RT8869A 4 ds8869a-00 may 2011 www.richtek.com vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 0 1 0 0 0 1 1 0 1.17500 0 1 0 0 0 1 1 1 1.16875 0 1 0 0 1 0 0 0 1.16250 0 1 0 0 1 0 0 1 1.15625 0 1 0 0 1 0 1 0 1.15000 0 1 0 0 1 0 1 1 1.14375 0 1 0 0 1 1 0 0 1.13750 0 1 0 0 1 1 0 1 1.13125 0 1 0 0 1 1 1 0 1.12500 0 1 0 0 1 1 1 1 1.11875 0 1 0 1 0 0 0 0 1.11250 0 1 0 1 0 0 0 1 1.10625 0 1 0 1 0 0 1 0 1.10000 0 1 0 1 0 0 1 1 1.09375 0 1 0 1 0 1 0 0 1.08750 0 1 0 1 0 1 0 1 1.08125 0 1 0 1 0 1 1 0 1.07500 0 1 0 1 0 1 1 1 1.06875 0 1 0 1 1 0 0 0 1.06250 0 1 0 1 1 0 0 1 1.05625 0 1 0 1 1 0 1 0 1.05000 0 1 0 1 1 0 1 1 1.04375 0 1 0 1 1 1 0 0 1.03750 0 1 0 1 1 1 0 1 1.03125 0 1 0 1 1 1 1 0 1.02500 0 1 0 1 1 1 1 1 1.01875 0 1 1 0 0 0 0 0 1.01250 0 1 1 0 0 0 0 1 1.00625 0 1 1 0 0 0 1 0 1.00000 0 1 1 0 0 0 1 1 0.99375 0 1 1 0 0 1 0 0 0.98750 0 1 1 0 0 1 0 1 0.98125 0 1 1 0 0 1 1 0 0.97500 0 1 1 0 0 1 1 1 0.96875 0 1 1 0 1 0 0 0 0.96250 0 1 1 0 1 0 0 1 0.95625 vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 0 1 1 0 1 0 1 0 0.95000 0 1 1 0 1 0 1 1 0.94375 0 1 1 0 1 1 0 0 0.93750 0 1 1 0 1 1 0 1 0.93125 0 1 1 0 1 1 1 0 0.92500 0 1 1 0 1 1 1 1 0.91875 0 1 1 1 0 0 0 0 0.91250 0 1 1 1 0 0 0 1 0.90625 0 1 1 1 0 0 1 0 0.90000 0 1 1 1 0 0 1 1 0.89375 0 1 1 1 0 1 0 0 0.88750 0 1 1 1 0 1 0 1 0.88125 0 1 1 1 0 1 1 0 0.87500 0 1 1 1 0 1 1 1 0.86875 0 1 1 1 1 0 0 0 0.86250 0 1 1 1 1 0 0 1 0.85625 0 1 1 1 1 0 1 0 0.85000 0 1 1 1 1 0 1 1 0.84375 0 1 1 1 1 1 0 0 0.83750 0 1 1 1 1 1 0 1 0.83125 0 1 1 1 1 1 1 0 0.82500 0 1 1 1 1 1 1 1 0.81875 1 0 0 0 0 0 0 0 0.81250 1 0 0 0 0 0 0 1 0.80625 1 0 0 0 0 0 1 0 0.80000 1 0 0 0 0 0 1 1 0.79375 1 0 0 0 0 1 0 0 0.78750 1 0 0 0 0 1 0 1 0.78125 1 0 0 0 0 1 1 0 0.77500 1 0 0 0 0 1 1 1 0.76875 1 0 0 0 1 0 0 0 0.76250 1 0 0 0 1 0 0 1 0.75625 1 0 0 0 1 0 1 0 0.75000 1 0 0 0 1 0 1 1 0.74375 1 0 0 0 1 1 0 0 0.73750 1 0 0 0 1 1 0 1 0.73125 to be continued
RT8869A 5 ds8869a-00 may 2011 www.richtek.com vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 1 0 0 0 1 1 1 0 0.72500 1 0 0 0 1 1 1 1 0.71875 1 0 0 1 0 0 0 0 0.71250 1 0 0 1 0 0 0 1 0.70625 1 0 0 1 0 0 1 0 0.70000 1 0 0 1 0 0 1 1 0.69375 1 0 0 1 0 1 0 0 0.68750 1 0 0 1 0 1 0 1 0.68125 1 0 0 1 0 1 1 0 0.67500 1 0 0 1 0 1 1 1 0.66875 1 0 0 1 1 0 0 0 0.66250 1 0 0 1 1 0 0 1 0.65625 1 0 0 1 1 0 1 0 0.65000 1 0 0 1 1 0 1 1 0.64375 1 0 0 1 1 1 0 0 0.63750 1 0 0 1 1 1 0 1 0.63125 1 0 0 1 1 1 1 0 0.62500 1 0 0 1 1 1 1 1 0.61875 1 0 1 0 0 0 0 0 0.61250 1 0 1 0 0 0 0 1 0.60625 1 0 1 0 0 0 1 0 0.60000 1 0 1 0 0 0 1 1 0.59375 1 0 1 0 0 1 0 0 0.58750 1 0 1 0 0 1 0 1 0.58125 1 0 1 0 0 1 1 0 0.57500 1 0 1 0 0 1 1 1 0.56875 1 0 1 0 1 0 0 0 0.56250 1 0 1 0 1 0 0 1 0.55625 1 0 1 0 1 0 1 0 0.55000 1 0 1 0 1 0 1 1 0.54375 1 0 1 0 1 1 0 0 0.53750 1 0 1 0 1 1 0 1 0.53125 1 0 1 0 1 1 1 0 0.52500 1 0 1 0 1 1 1 1 0.51875 1 0 1 1 0 0 0 0 0.51250 1 0 1 1 0 0 0 1 0.50625 vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 1 0 1 1 0 0 1 0 0.50000 1 1 1 1 1 1 1 0 off 1 1 1 1 1 1 1 1 off
RT8869A 6 ds8869a-00 may 2011 www.richtek.com functional pin description pin no. pin name pin function 1 vrsel load line adjustment enable pin. connect this pin to vtt and gnd to disable and enable load line adjustment function respectively. 2 vr_rdy vr ready indication. 3 ss soft-start ramp slope set pin. connect this pin to fbrtn by a capacitor to adjust soft-start slew rate. 4 en chip enable pin. pull this pin higher than 0.8v to enable the pwm controller. 5 dac dac output pin. connect a resistor from this pin to eap pin for setting the load line slope. 6 eap non-inverting input of error-amplifier pin. connect a resistor from this pin to dac pin to set the load line slope. 7 fb inverting input of error amplifier pin. 8 comp compensation pin. output of error amplifier and input of pwm comparator. 9, 10 csp, csn input of current sensing amplifier. the sensed current is for droop control and over current protection. 11 imax output current indication. connect a resistor from this pin to gnd to set the over current protection threshold. 12 vr_shdn vr_shdn indication. 13 ps1 dynamic phase control threshold input 1. connect this pin to gnd by a resistor to set dynamic phase control threshold. 14, 15 isen2, isen1 phase current sense pins for phase 2 and phase 1. per phase current signal is sensed via the voltage across low side mosfets r ds(on) for current balance. 16 rt switching frequency set pin. connect this pin to gnd via a resistor to adjust switching frequency. 17 vcc5 internal 5v regulator output. 18 tb transient boost pin. this pin along with the vout pin sets the transient boost function. 19 vout positive voltage sensing pin. this pin is the positive node of the differential voltage sensing and along with tb pin sets the transient boost function. 20 tm thermal monitoring input pin. connect a resistive voltage divider with ntc to detect temperature. 21 vr_hot thermal monitoring output pin. connect a resistor to vtt for vr_hot signal assertion. 22, 31 boot2, boot1 bootstrap power pins for phase 2 and phase 1. this pin powers the high side mosfets drivers. connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. 23, 30 ugate2, ugate1 upper gate drivers for phase 2 and phase 1. this pin drives the gate of the high side mosfets. 24, 29 phase2, phase1 switch nodes of high side driver 2 and driver 1. connect this pin to high side mosfets sources together with the low side mosfets drains and inductor. 25, 28 lgate2, lgate1 lower gate drivers for phase 2 and phase 1. this pin drives the gate of low side mosfets. to be continued
RT8869A 7 ds8869a-00 may 2011 www.richtek.com pin no. pin name pin function 26 vcc12b supply input pin. this pin supplies current for phase 2 gate driver. 27 vcc12a supply input pin. this pin supplies current for phase 1 gate driver and control circuits. 32 to 39 vid7 to vid0 voltage identification input for dac. 40 fbrtn return ground pin. this pin is negative node of the differential remote voltage sending. 41 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. function block diagram mosfet driver boot1 ugate1 phase1 lgate1 + - p w m 1 mosfet driver boot2 ugate2 phase2 lgate2 + - p w m 2 vcc12b transient response enhancement - + o v p v e a p + 1 6 0 m v - + u v p v e a p - 3 0 0 m v + - o c p 1 . 2 v + - e a current balance i m a x c o m p e a p f b + - c s n c s p + - s/h + - s/h v o u t t b i s e n 2 i s e n 1 modulator waveform generator thermal monitor table generator por 5v regulator soft- start vcc12a vcc5 vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vrsel fbrtn en s s v r _ r d y d a c rt ps1 + - v d c tm vr_hot gnd i x i x i s e n 2 i s e n 1 vr_shdn load line adjustment
RT8869A 8 ds8869a-00 may 2011 www.richtek.com electrical characteristics parameter symbol test c onditions min typ max unit supply input supply current i cc12 -- 6 -- ma vcc5 supply voltage v cc5 i load = 10ma 4.9 5 5.1 v vcc5 output sourcing i vcc5 10 -- -- ma soft-start current i ss1 vr _r dy = low 68 80 92 a vid change current i ss2 vr_rdy = high 135 160 185 a transient boost sinking current i tb 9 10 11 a thermal management vr_hot threshold level 41 43 48 %v cc5 v r_h ot hysteresis -- 7 -- %v cc5 vr_shdn threshold level 30 32 34 %v cc5 to be continued recommended operating conditions (note 4) z supply input voltage (v cc12a, vcc12b) --------------------------------------------------- 10.8v to 13.2v z junction temperature range --------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range --------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply input voltag e (vcc12 a, vcc12b) --------------------------------------------------- ? 0.3v to 15v z bootx to phasex -------------------------------------------------------------------------------- ? 0.3v to 15v z phasex to gnd dc ------------------------------------------------------------------------------------------------------ ? 2v to 15v < 20ns ------------------------------------------------------------------------------------------------- ? 5v to 30v z ugatex to gnd ------------------------------------------------------------------------------------ (v phasex ? 0.3v) to (v bootx + 0.3v) < 20ns ------------------------------------------------------------------------------------------------ (v phasex ? 5v) to (v bootx + 5v) z lgatex to gnd ------------------------------------------------------------------------------------ (gnd ? 0.3v) to (v cc12x + 0.3v) < 20ns ------------------------------------------------------------------------------------------------ (gnd ? 5v) to (v cc12x + 5v) z power dissipation, p d @ t a = 25 c wqfn ? 40l 5x5 ------------------------------------------------------------------------------------- 2.778w z package thermal resistance (note 2) wqfn ? 40l 5x5, ja ------------------------------------------------------------------------------- 36 c/w wqfn ? 40l 5x5, jc ------------------------------------------------------------------------------- 6 c/w z junction temperature ------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ------------- ---------------------------------------------------------- 2kv mm (machine mode) ------------------------------------------------------------------------------- 200v (v cc12x = 12v, t a = 25 c, unless otherwise specified)
RT8869A 9 ds8869a-00 may 2011 www.richtek.com parameter symbol test conditions min typ max unit power on reset vcc12 rising threshold v cc12rth vcc12 rising 9.2 9.6 10 v vcc12 hysteresis v cc12hys vcc12 falling -- 0.9 -- v vcc5 rising threshold v cc5rth vcc5 rising 4.4 4.6 4.8 v vcc5 hysteresis v cc5hys vcc5 falling -- 0.4 -- v enable control logic-high v ih 0.8 -- -- en input threshold voltage logic-low v il -- -- 0.4 v oscillator switching frequency f osc r rt = 24k , for 2 phase operation 270 300 330 khz adjustable frequency range 50 -- 1000 khz ramp amplitude (note 5) 3.5 4 4.5 v maximum duty (note 5) 61 66 71 % rt pin voltage v rt 1.55 1.6 1.65 v reference voltage and dac 1v to 1.6v ? 0.5 -- 0.5 % 0.8v to 1v ? 8 -- 8 mv dac accuracy 0.5v to 0.8v ? 10 -- 10 mv logic-high v ih 0.8 -- -- dac input threshold voltage (vid0 to vid7, vrsel) logic-low v il -- -- 0.4 v error amplifier dc gain a dc no load -- 80 -- db gain bandwidth gbw c load = 10pf -- 10 -- mhz slew rate sr c load = 10pf 10 -- -- v/ s output voltage range v comp 0.5 3.6 v maximum current i ea_slew 300 -- -- a current sense maximum current i gmmax 100 -- -- a input offset voltage v oscs ? 1 0 1 mv imax current mirror accuracy i max / i avg , 2 phase operation 368 400 432 % droop current mirror accuracy i drp / i av g , 2 phase operation 368 400 432 % gate driver ugate drive source r ugatesr v boot ? v phase = 8v 250ma source current -- 2 4 ugate drive sink r ugatesk v boot ? v phase = 8v 250ma sink current -- 1 2 lgate drive source r lgatesr v lgate = 8v -- 2 4 lgate drive sink r lgatesk 250ma sink current -- 0.8 1.6 to be continued
RT8869A 10 ds8869a-00 may 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high-effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. guaranteed by design. parameter symbol test conditions min typ max unit protection total current protection threshold v imax 1.1 1.2 1.3 v over voltage threshold v ovp v fb ? v eap 350 390 430 mv under voltage threshold v uvp v fb ? v eap ? 380 ? 300 ? 250 mv over temperature protection threshold (note 5) 145 150 175 c over temperature protection hysteresis -- 20 -- c output pin capability vr_hot sinking capability v vr_hot i vr _hot = 4ma -- 0.05 0.2 v vr_rdy sinking capability v vr_rdy i vr_rdy = 4ma -- 0.05 0.2 v vr_shdn sinking capability v vr_shdn i vr _sh dn = 4ma -- 0.05 0.2 v
RT8869A 11 ds8869a-00 may 2011 www.richtek.com typical operating characteristics vcc5 supply voltage vs. temperature 4.94 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 -50-250 255075100125 temperature ( c) vcc5 supply voltage (v) frequency vs. temperature 294 296 298 300 302 304 306 308 -50 -25 0 25 50 75 100 125 temperature ( c) frequency (khz) 1 power on from en en (2v/div) vr_rdy (1v/div) ugate1 (20v/div) time (400 s/div) v out (1v/div) v in = 12v, i out = 30a power off from en time (40 s/div) v in = 12v, i out = 30a en (2v/div) vr_rdy (1v/div) ugate1 (20v/div) v out (1v/div) dynamic output voltage control time (20 s/div) v out (500mv/div) utate1 (20v/div) vid5 (2v/div) v in = 12v, i out = 0a, vid = 1v to 1.2v utate2 (20v/div) inductor current vs. load current 0 5 10 15 20 25 30 20 25 30 35 40 45 50 55 60 load current (a) inductor current (a) 1 phase 1 phase 2
RT8869A 12 ds8869a-00 may 2011 www.richtek.com time (20 s/div) dynamic output voltage control time (10 s/div) load step up time (400 s/div) uvp r imax = 36k time (400 s/div) ocp time (10 s/div) load step down time (400 s/div) ovp v out (500mv/div) utate1 (20v/div) vid5 (2v/div) v in = 12v, i out = 0a, vid = 1.2v to 1v utate2 (20v/div) v out (100mv/div) utate1 (20v/div) i out (50a/div) v in = 12v, r ll = 1m utate2 (20v/div) v out (100mv/div) utate1 (20v/div) i out (50a/div) v in = 12v, r ll = 1m utate2 (20v/div) v fb (1v/div) utate1 (20v/div) eap (1v/div) v dac = 1v, v fb = 1v to 1.5v, i out = 0a ltate2 (20v/div) v fb (1v/div) utate1 (20v/div) eap (1v/div) v dac = 1v, v fb = 1v to 0.5v, i out = 0a ltate2 (20v/div) v out (1v/div) utate1 (20v/div) i out (50a/div) ltate2 (20v/div)
RT8869A 13 ds8869a-00 may 2011 www.richtek.com application information the RT8869A is an advanced 2/1 phase synchronous buck controller with 2 integrated mosfet drivers. it integrates an 8-bit dac that supports intel vr11.x vid tables. supply voltage and por there are three supply voltage pins built in the RT8869A: vcc12a/vcc12b and vcc5. vcc12a/vcc12b are power input pins that receive an external 12v voltage for the embedded driver logic operation. vcc5 is a power output pin which is the output of an internal 5v ldo regulator. the 5v ldo regulator regulates vcc12a to generate a 5v voltage source for internal gate logic and external circuit biasing, e.g., ocp biasing. since the vcc5 voltage is regulated, the variation of vcc5 (2%) will be much smaller than platform atx + 5v (5% to 7%). the maximum supply current of vcc5 is 10ma, which is designed only for controller circuit biasing. the recommended configuration of the RT8869A supply voltages is as follows: platform atx + 12v to the vcc12a/ vcc12b pins, and decoupling capacitors on the vcc12a/ vcc12b and vcc5 pins (minimum 0.1 f). the initialization of the RT8869A requires all the voltage o n vcc12a/vcc12b and vcc5 to be read y. since vcc5 is regulated intern ally from vcc12a, the vcc5 voltage will be ready (>4.6v) after vcc12a reaches about 7v, so there is no power sequence problem between vcc12a/vcc12b and vcc5. after vcc5 > 4.6v and vcc12a/vcc12b > 9.6v, the internal power-on-reset (por) signal goes high. this por signal indicates the power supply voltages are all ready. when por = high and en = high, the RT8869A initiates soft-start sequence. when por = low, the RT8869A will try to turn off both high side and low side mosfets to prevent catastrophic failure. por vcc12a/ vcc12b + - cmp + - cmp por : power on reset 9.6v 4.6v vcc5 figure 1. circuit for power ready detection switching frequency the switching frequency of the RT8869A is set by an external resistor connected from the rt pin to gnd. the frequency follows the graph in figure 2. figure 2. switching frequency vs. r rt resistance soft-start the v out soft-start slew rate is set by a capacitor from the ss pin to fbrtn. before power on reset (por = low), the ss pin is held at gnd. after power on reset (por = high, en = high) and an extra delay of 1600 s (t1), the controller initiates ramping up. v out will always trace v eap during normal operation of the RT8869A, where v eap is the positive input of the error amplifier, which can be described as v eap = v dac ? v droop . (the definition of v droop will be described later in the load line section). the first ramping up duration of v out (t2) ramps v out to v boot . after v out ramps to v boot , the RT8869A stays in this state for 800 s (t3), waiting for a valid vid code sent by the cpu. after receiving the valid vid code, v out continues ramping up or down to the voltage specified by vid code. after v out ramps to v eap = v dac ? v droop , the RT8869A stays in this state for 1600 s (t5) and then asserts vr_rdy = high. the ramping slew rate of t2 and t4 is controlled by the external capacitor connected to ss pin. the voltage of the ss pin will always be veap+0.7v, where the mentioned 0.7v is the typical turn-on threshold of an internal power switch. before vr_rdy = high, the slew rate of v eap is limited to 80 a/c ss . when vr_rdy 0 200 400 600 800 1000 1200 0 20406080 r rt (k ? ) switching frequency (khz) 1
RT8869A 14 ds8869a-00 may 2011 www.richtek.com = high, the slew rate of v eap is limited to 160 a/c ss , which is 2 times faster than the soft-start slew rate for dynamic vid feature. the soft start waveform is shown in figure 2. figure 3. circuit for soft-start and voltage control loop figure 4. soft-start waveforms vcc12 vcc5 9.6v 4.6v v en ss vr_rdy t1 t2 t3 t4 t5 v out v boot dynamic vid the RT8869A can accept vid input changing while the controller is running. this allows the output voltage (v out ) to change while the dc/dc converter is running and supplying current to the load. this is commonly referred to as vid on-the-fly (otf). a vid otf can occur under either light or heavy load conditions. the cpu changes the vid inputs in multiple steps from the start code to the finish code. this change can be positive or negative. theoretically, v out should follow v dac which is a staircase waveform, but in real application, the bandwidth of the converter is finite while the staircase waveform needs infinite bandwidth to follow. thus, undesired v out overshoot (when v dac changes up) or undershoot (when v dac changes down) is often observed in this type of design. however, for the RT8869A, as mentioned before in the soft-start section, v dac slew rate is limited by i ss2 /c ss when vr_rdy = high. this slew rate limiter works as a low-pass filter of v dac and makes the bandwidth of v dac waveform finite. by smoothening the v dac staircase waveform, v out will no longer overshoot or undershoot. on the other hand, c ss will increase the settling time of v out during vid otf. in most cases, a 5nf to 30nf ceramic capacitor will be suitable for c ss . output voltage differential sensing the RT8869A uses a high gain low offset error amplifier for differential sensing. the cpu voltage is sensed between the fb and fbrtn pins. a resistor (r fb ) connects fb pin with the positive remote sense pin of the cpu (v cc_sns ), while the fbrtn pin connects directly to the negative remote sense pin of the cpu (v ss_sns ). the error amplifier compares v eap (= v dac ? v droop ) with the v fb to regulate the output voltage. transient boost in steady state, the voltage of v out is controlled to be very close to v eap , however a load step transient from light load to heavy load could cause v out to be lower than v eap by several tens of mv. in conventional buck converter design (without non-linear control) for cpu vr application, due to limited control bandwidth, it is hard for the vr to prevent v out undershoot during quick load transient from light load to heavy load. hence, the RT8869A builds in a t1 is the delay time from power on reset state to the beginning of v out rising. t2 is the soft-start time from v out = 0 to v out = v boot . t3 is the dwelling time for v out = v boot . t4 is the soft-start time form v out = v boot to v out = v dac . t5 is the vr_rdy delay time. t1 = 1600 s + 0.7v x c ss /80 a. t2 = v boot x c ss /80 a. t3 800 s. t4 |v dac ? v boot | x c ss /80 a. t5 1600 s. soft-start circuit i ss eap (error amp positive input) soft- start current (i ss ) is limited and variant r2 r1 r3 c2 c1 c3 v out fb comp c ss + - ea i x (output current sensed signal) r droop eap dac dac
RT8869A 15 ds8869a-00 may 2011 www.richtek.com state-of-the-art transient boost function which detects load transient by monitoring v out . if v out suddenly droops below ? v tb ? the transient boost signal rises up and the RT8869A turns on all high side mosfets and turns off all low side mosfets. the voltage difference ? v out ? v tb ? is set by following equation : v out ? v tb = 10 a x r tb . sensitivity of the transient boost can be adjusted by varying the values of c fb and r fb . smaller r fb and/or larger c fb will make transient boost easier to be triggered. figure 5 shows the circuit and typical waveforms. figure 5. (b) typical waveforms + - 10a transient boost r tb c tb v out tb vout figure 5. (a) transient boost circuit output current sensing the RT8869A provides a low input offset current-sense amplifier (csa) to monitor the output current. the output current of csa (i x ) is used for load line control, dynamic phase control and over current protection. in this average inductor current sensing topology, r s and c s must be set according to the equation below : xntc ss s requ = r //r rc l dcr r n requ = + figure 6 is the current sense circuit. where the constant n is a set maximum operation phase number, not affected by the dynamic phase control machine. then, the output current of csa will follow the equation below : out x csn idcr i nr = figure 6. circuit for current sensing load line the RT8869A utilizes inductor dcr current sense technique for load line control function. the sensed output current is proportionally mirrored from the i x signal to the r droop resistor to establish the voltage of v droop . v droop subtracted from v dac generates v eap . the voltage control loop is shown in figure 3. because i x is a ptc (positive temperature coefficient) current, an ntc (negative temperature coefficient) resistor is needed to connect in parallel with the capacitor c s . if the ntc resistor is properly selected to compensate the temperature coefficient of i x , the v droop voltage will be proportional to i out without temperature effect. in the RT8869A, the positive input of error amplifier is v eap and v out will follow ? v dac ? v droop ? . thus, the output voltage which decreases linearly with i out is obtained. the load line is defined as : out droop droop out out csn vv dcrr 4 ll(load line) ii nr ? == = ? basically, the resistance of r droop sets the resistance of the load line. the temperature coefficient of r droop compensates the temperature effect of the load line. connecting vrset pin to gnd can enable load line adjustment function. meanwhile, the current i x is decreased by 10mv/r csn , and the minimum output current sensing range is also reduced by 10mv/r csn . i out v out transient boost l dcr l dcr r s r s r x + - r csn csn csp csa ntc (current sense amplifier) i x ph1 ph2 c out r l v core i out c s load line adjustment
RT8869A 16 ds8869a-00 may 2011 www.richtek.com where v dc is the offset voltage for the current balance circuit. in figure 7, the phase current sense signals i senx are used to raise or lower the internal sawtooth waveforms (ramp [1] and ramp [2]) which are compared with error amplifier output (comp) to generate a pwm signal. the raised sawtooth waveform will decrease the pwm duty of the corresponding phase current and the lowered sawtooth waveform will increase the pwm duty of the corresponding phase current. eventually, current flowing through each phase will be balanced. phasex dson dc senx senx irv i = r + figure 7. circuit for current balance dynamic phase control capability the RT8869A has the ability to automatically control its phase number according to the total load current. connect a resistor to ground at ps1 pin to set the 1-2 phase transition threshold, v ps1 . the voltage at imax pin (v imax ) represents total current information, and the RT8869A will compare v imax with v ps1 to determine the number of operating phases. figure 8 shows the typical connections of ps1 pin for settin g the dynamic phase control thresholds. figure 8. circuit for dynamic phase control and vr shutdown table 2. dynamic phase control v imax phase number v ps1 > 1.6v v imax = don?t care forced 1 0.8v < v ps1 < 1.6v v imax = don?t care forced 2 > v ps1 2 < v ps1 1 r sen1 r sen2 current balance isen1 isen2 ph1 ph2 after setting the voltage at the ps1 pin, the RT8869A will continuously compare v imax and v ps1 after por. once the v imax enters each voltage state mentioned in table 2, the RT8869A will automatically change its operation phase number. see table 2 for the dynamic phase control mechanism. for example, if v ps1 = 0.3v, the RT8869A will operate in 2 phase operation when v imax = 0.9v, and 1 phase operation when v imax = 0.1v. there are two states mentioned in table 2 that the RT8869A will be forced not to change its operating phase number, and the v imax voltage is meaningless for dynamic phase control circuit under these conditions. over current protection (ocp) when v imax is higher than 1.2v, the over current protection is triggered with 100 s delay to prevent false trigger, and the short circuit ocp level is designed at 1.6v with 10 s delay. the controller will turn off all high side / low side mosfets to protect cpu. note that, the ocp level does not change according to different operating phase numbers. over voltage protection (ovp) the over voltage protection monitors the output voltage via the fb pin. once v fb exceeds ? v eap + 390mv ? , ovp is triggered and latched. the RT8869A will turn on low side mosfet and turn off high side mosfet to protect cpu. under voltage protection (uvp) the under-voltage protection monitors the output voltage via the fb pin. once vfb is lower than ? v eap ? 300mv ? , uvp is triggered and latched. the RT8869A will turn off all high side / low side mosfets to protect cpu. current balance the RT8869A sensed per phase current signal i senx via the voltages on the low side mosfets switch on resistance (r ds(on) ) for current balance as shown in figure 7, in which i senx is defined as : + - v i m a x 1 0 a dynamic phase control ps1
RT8869A 17 ds8869a-00 may 2011 www.richtek.com the esr zero is contributed by the esr associated with the output capacitance. note that this requires the output capacitor to have enough esr to satisfy stability requirements. the esr zero of the output capacitor is expressed as the following equation : lc out out 1 f 2l c = amplifier output). this transfer function is dominated by a dc gain, a double pole, and an esr zero as shown in figure 10. the dc gain of the modulator is the input voltage (vin) divided by the peak-to-peak oscillator voltage v osc . the output lc filter introduces a double pole, 40db/ decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. the resonant frequency of the lc filter is expressed as: esr out 1 f 2c esr = figure 10. bode plot of loop gain 2) design of the compensator a well-designed compensator regulates the output voltage to the reference voltage v ref with fast transient response and good stability. in order to achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. the goal of the compensation network is to provide adequate phase margin (usually greater than 45 ) and the highest bandwidth (0db crossing frequency, f c ) possible. it is also recommended to manipulate the loop frequency response such that its gain crosses over 0db at a slope of ? 20db/ dec. according to figure 10, the location of poles and zeros are : = z1 1 f 2r2c1 loop compensation the RT8869A is a voltage mode controller and requires external compensation. to compensate a typical voltage mode buck converter, there are two ordinary compensation schemes, commonly known as type-ii compensator and type-iii compensator. the choice of using type-ii or type- iii compensator lies with the platform designers, and the main concern deals with the position of the capacitor esr zero and mid-frequency to high frequency gain boost. typically, the esr zero of output capacitor will tend to stabilize the effect of output lc double poles. hence, the position of the output capacitor esr zero in frequency domain may influence the design of voltage loop compensation. figure 9 shows a typical control loop using type-iii compensator. below is the compensator design procedure. figure 9. compensation circuit 1) modulator characteristic the modulator consists of the pwm comparator and power stage. the pwm comparator compares the error amplifier output (comp) with oscillator (osc) sawtooth wave to provide a pulse-width modulated (pwm) gate-driving signal. the pwm wave is smoothed out by the output filter, l out and c out . the output voltage (v out ) is sensed and fed to the inverting input of the error amplifier. the modulator transfer function is the small-signal transfer function of v out /v comp (output voltage over the error - + + - osc v osc z fb z in v in driver driver ref pwm comparator comp ea + - ref ea z fb z in v out fb comp c1 c2 c3 r1 r2 r3 esr c out v out l f p3 f p2 f z2 f z1 gain log log frequency 0 f lc f esr f c modulator gain compensation gain closed loop gain
RT8869A 18 ds8869a-00 may 2011 www.richtek.com = = = = + z2 p1 p2 p3 1 f 2r2c1 f0 1 f 2c3r3 1 f c1 c2 r2 2 c1 c2 generally, f z1 and f z2 are designed to cancel the double pole of the modulator. usually, place f z1 at a fraction of f lc , and place f z2 at f lc . f p2 is usually placed at f esr to cancel the esr zero, and f p3 is placed below the switching frequency to cancel high frequency noise. for a given bandwidth, r2, f z1 , f z2 , f p2 , f p3 , then z1 mod@bw c z2 p2 p3 1 c1 2r2f g c3 2fr2 1 r1 2f c3 1 r3 2f c3 1 c2 2 f c1 r2 1 = = = = = ? thermal monitoring (vr_hot&vr_shdn) the RT8869A provides thermal monitoring function via sensing the tm pin voltage, and which can set 2 thresholds to indicate ambient temperatures through the voltage divider r1 and r ntc . the voltage of tm is typically set to be higher than 0.5 x vcc5 when ambient temperature is lower than vr_hot & vr_shdn assertion target. however, when ambient temperature rises, tm voltage will fall, and the vr_hot signal will be set to high if tm voltage droops below 0.43 x vcc5. furthermore, if the temperature continues to rise and the tm voltage is lower than 0.32 x vcc5, the controller will shutdown and pull the vr_shdn signal to low. accordingly, vr_hot will be reset when tm voltage rises above 0.5 x vcc5, but the controller will not reboot once thermal shutdown occurs. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the figure 11. derating curve for RT8869A package maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT8869A, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn- 40l 5x5 packages, the thermal resistance, ja , is 36 c/ w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (36 c/w) = 2.778w for wqfn-40l 5x5 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT8869A package, the derating curve in figure 11 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT8869A 19 ds8869a-00 may 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 4.950 5.050 0.195 0.199 d2 3.250 3.500 0.128 0.138 e 4.950 5.050 0.195 0.199 e2 3.250 3.500 0.128 0.138 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 40l qfn 5x5 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 d e d2 e2 l b a a1 a3 e 1 see detail a

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